In the electric industry, memory devices are of vital applications in various kinds of system like computers and other peripherals. With the increasing demand on system operating speed and performance, more and more high speed and reliable memory devices are employed. DRAM (dynamic random access memory) is one of the most important devices in the semiconductor devices. In last decade, DRAM cells and chips are widely applied in computer systems for it's fast and reliable characteristics.
In the semiconductor manufacturing process of making memory chips, numerous processes are performed to make a great number of memory chips on a single wafer. Some defects may be found under the complex manufacturing steps and densely packed circuits. The undesired defects cause some of the memory chips to be defective ones and thus influence the yield of the products. However, most of the defective chips are only partially defected and a lot of workable cells are still left on the chips. By the design and the addition of external compensating circuits, two or more memory chips can be combined as a workable, defect-free one. Most of the partially defective chips can be merged to produce workable memory chips with undamaged functionality. Thus the cost can be reduced and the yield can be increased by reworking the defective chips to a workable one.
In system applications, DRAM can be classified into several types, like fast page mode DRAM, EDO (extended data output) DRAM, and SDRAM (synchronous DRAM). Various compensating method can be employed for combining defective fast page mode DRAM or EDO DRAM chips. In the U.S. Pat. No. 5,640,353 to the applicant of the present invention, an external compensation apparatus and method for fail bit DRAM is disclosed. The method is implemented by transforming and controlling address bits to replace defective bits. Referring to FIG. 1, the compensation apparatus has a tag address region 304, a compensation data region 305, a control logic 306, and a comparator 300. Thus bit defects of DRAM devices can be compensated to ensure the functionality of the system.
However, the address bit transforming and controlling scheme of the prior art method can not be applied on SDRAMs. In general, the operating mode of SDRAM cells are programmed by internal registers. The system has to program the registers of SDRAM cells by an address bus before operation. If the prior art external compensating scheme is used, a portion of the address of the SDRAM is fixed at a constant high or a constant low state. Some of the address are occupied and can not be used to program the internal registers. Thus the combined SDRAMs can not be operated by the conventional compensation scheme.